4    Floating-Point Instruction Set

This chapter describes the assembler's floating-point instructions. See Chapter 3 for a description of the integer instructions. For details on the instruction set beyond the scope of this manual, refer to the Alpha Architecture Reference Manual.

The assembler's floating-point instruction set contains the following classes of instructions:

• Load and store instructions (Section 4.2)

• Arithmetic instructions. (Section 4.3)

• Relational instructions (Section 4.4)

• Move instructions (Section 4.5)

• Control instructions (Section 4.6)

• Special-purpose instructions (Section 4.7)

A particular floating-point instruction may be implemented in hardware, software, or a combination of hardware and software.

Tables in this chapter show the format for each instruction in the floating-point instruction set. The tables list the instruction names and the forms of operands that can be used with each instruction. The specifiers used in the tables to identify operands have the following meanings:

Operand Specifier	Description
address	A symbolic expression whose effective value is used as an address.
d_reg	Destination register. A floating-point register that receives a value as a result of an operation.
2d_reg/s_reg	One floating-point register that is used as both a destination register and a source register.
label	A label that identifies a location in a program.
s_reg,s_reg1,s_reg2	Source registers. Floating-point registers whose contents are to be used in an operation.
val_expr	An expression whose value is a floating-point constant.

The following terms are used to discuss floating-point operations:

Term	Meaning
Infinite	A value of +infinity or -infinity.
Infinity	A symbolic entity that represents values with magnitudes greater than the largest magnitude for a particular format.
Ordered	The usual result from a comparison, namely: less than (<), equal (=), or greater than (>).
NaN	Symbolic entities that represent values not otherwise available in floating-point formats. (NaN is an acronym for not-a-number.)
Unordered	The condition that results from a floating-point comparison when one or both operands are NaNs.

There are two kinds of NaNs:

• Quiet NaNs represent unknown or uninitialized values.

• Signaling NaNs represent symbolic values and values that are too big or too precise for the format. Signaling NaNs raise an invalid-operation exception whenever an operation is attempted on them.

4.1    Background Information on Floating-Point Operations

Topics addressed in the following sections include:

• Floating-point data types (Section 4.1.1)

• The floating-point control register (Section 4.1.2)

• Floating-point exceptions (Section 4.1.3)

• Floating-point rounding modes (Section 4.1.4)

• Floating-point instruction qualifiers (Section 4.1.5)

4.1.1    Floating-Point Data Types

Floating-point instructions operate on the following data types:

• D_floating (VAX double precision, limited support)

• F_floating (VAX single precision)

• G_floating (VAX double precision)

• S_floating (IEEE single precision)

• T_floating (IEEE double precision)

• Longword integer and quadword integer

Figure 4-1 shows the memory formats for the single- and double-precision floating-point data types.

Figure 4-1: Floating-Point Data Formats

4.1.2    Floating-Point Control Register

The floating-point control register (FPCR) contains status and control information. It controls the arithmetic rounding mode of instructions that specify dynamic rounding (d qualifier - see Section 4.1.5 for information on instruction qualifiers) and gives a summary for each exception type of the exception conditions detected by the floating-point instructions. It also contains an overall summary bit indicating whether an exception occurred.

Figure 4-2 shows the format of the floating-point control register.

Figure 4-2: Floating-Point Control Register

The fields of the floating-point control register have the following meaning:

Bits	Name	Description
63	sum	Summary - records the bitwise OR of the FPCR exception bits (bits 57 to 52).
62-60	raz/ign	Read-As-Zero - ignored when written.
59-58	dyn	Dynamic Rounding Mode - indicates the current rounding mode to be used by an IEEE floating-point instruction that specifies dynamic mode (d qualifier). The bit assignments for this field are as follows: 00 - Chopped rounding mode 01 - Minus infinity 10 - Normal rounding 11 - Plus infinity
57	iov	Integer overflow.
56	ine	Inexact result.
55	unf	Underflow.
54	ovf	Overflow.
53	dze	Division by zero.
52	inv	Invalid operation.
51-0	raz/ign	Read-As-Zero - ignored when written.

The floating-point exceptions associated with bits 57 to 52 are described in Section 4.1.3.

4.1.3    Floating-Point Exceptions

Six exception conditions can result from the use of floating-point instructions. All of the exceptions are signaled by an arithmetic exception trap. The exceptions are as follows:

• Invalid Operation - An invalid-operation exception is signaled if any operand of a floating-point instruction, other than cmptxx, is nonfinite. (The cmptxx instruction operates normally with plus and minus infinity.) This trap is always enabled. If this trap occurs, an unpredictable value is stored in the destination register.

• Division by Zero - A division-by-zero exception is taken if the numerator does not cause an invalid-operation trap and the denominator is zero. This trap is always enabled. If this trap occurs, an unpredictable value is stored in the destination register.

• Overflow - An overflow exception is signaled if the rounded result exceeds the largest finite number of the destination format. This trap is always enabled. If this trap occurs, an unpredictable value is stored in the destination register.

• Underflow - An underflow exception occurs if the rounded result is smaller than the smallest finite number of the destination format. This trap can be disabled. If this trap occurs, a true zero is always stored in the destination register.

• Inexact Result - An inexact-result exception occurs if the infinitely precise result differs from the rounded result. This trap can be disabled. If this trap occurs, the normal rounded result is still stored in the destination register.

• Integer Overflow - An integer-overflow exception occurs if the conversion from a floating-point or integer format to an integer format results in a value that is outside of the range of values representable by the destination format. This trap can be disabled. If this trap occurs, the true result is truncated to the number of bits in the destination format and stored in the destination register.

4.1.4    Floating-Point Rounding Modes

If a true result can be exactly represented in a floating-point format, all rounding modes map the true result to that value.

The following abbreviations are used in the descriptions of rounding modes provided in this section:

• LSB (least significant bit) - For a positive representable number, A, whose fraction is not all ones: A + 1 LSB is the next-larger representable number, and A + 1/2 LSB is exactly halfway between A and the next larger representable number.

• MAX - The largest noninfinite representable floating-point number.

• MIN - The smallest nonzero representable normalized floating-point number.

For VAX floating-point operations, two rounding modes are provided and are specified in each instruction:

• Normal rounding (biased)

  • Maps the true result to the nearest of two representable results, with true results exactly halfway between mapped to the larger in absolute value. (Sometimes referred to as biased rounding away from zero.)

  • Maps true results >= MAX + 1/2 LSB in magnitude to an overflow

  • Maps true results < MIN - 1/2 LSB in magnitude to an underflow

• Chopped rounding

  • Maps the true result to the smaller in magnitude of two surrounding representable results

  • Maps true results >= MAX + 1 LSB in magnitude to an overflow

  • Maps true results < MIN in magnitude to an underflow

For IEEE floating-point operations, four rounding modes are provided:

• Normal rounding (unbiased round to nearest)

  • Maps the true result to the nearest of two representable results, with true results exactly halfway between mapped to the one whose fraction ends in 0. (Sometimes referred to as unbiased rounding to even.)

  • Maps true results >= MAX + 1/2 LSB in magnitude to an overflow

  • Maps true results < MIN - 1/2 LSB in magnitude to an underflow

• Rounding toward minus infinity

  • Maps the true results to the smaller of two surrounding representable results

  • Maps true results > MAX in magnitude to an overflow

  • Maps positive true results < +MIN to an underflow

  • Maps negative true results >= -MIN + 1 LSB to an underflow

• Chopped rounding (round toward zero)

  • Maps the true result to the smaller in magnitude of two surrounding representable results

  • Maps true results >= MAX + 1 LSB in magnitude to an overflow

  • Maps nonzero true results < MIN in magnitude to an underflow

• Rounding toward plus infinity

  • Maps the true results to the larger of two surrounding representable results

  • Maps true results > MAX in magnitude to an overflow

  • Maps positive results <= +MIN - 1 LSB to an underflow

  • Maps negative true results > -MIN to an underflow

The first three of the IEEE rounding modes can be specified in the instruction. The last mode, rounding toward plus infinity, can be obtained by setting the floating-point control register (FPCR) to select it and then specifying dynamic rounding mode in the instruction.

Dynamic rounding mode uses the IEEE rounding mode selected by the FPCR and is described in Section 4.1.2. Dynamic rounding can be used with any of the IEEE rounding modes.

Alpha IEEE arithmetic does rounding before detecting overflow or underflow.

4.1.5    Floating-Point Instruction Qualifiers

Many of the floating-point instructions accept a qualifier that specifies rounding and trapping modes.

The following table lists the rounding mode qualifiers. See Section 4.1.4 for a detailed description of the rounding modes.

	Rounding Mode	Qualifier
VAX Rounding Mode
	Normal rounding	(no modifier)
	Chopped	c
IEEE Rounding Mode
	Normal rounding	(no modifier)
	Plus infinity	d (ensure that the dyn field of the FPCR is 11)
	Minus infinity	m
	Chopped	c

The following table lists the trapping mode qualifiers. See Section 4.1.3 for a detailed description of the exceptions.

	Trapping Mode	Qualifier
VAX Trap Mode
	Imprecise, underflow disabled	(no modifier)
	Imprecise, underflow enabled	u
	Software, underflow disabled	s
	Software, underflow enabled	su
VAX Convert-to-Integer Trap Mode
	Imprecise, integer overflow disabled	(no modifier)
	Imprecise, integer overflow enabled	v
	Software, integer overflow disabled	s
	Software, integer overflow enabled	sv
IEEE Trap Mode
	Imprecise, underflow disabled, inexact disabled	(no modifier)
	Imprecise, underflow enabled, inexact disabled	u
	Software, underflow enabled, inexact disabled	su
	Software, underflow enabled, inexact enabled	sui
IEEE Convert-to-integer Trap Mode
	Imprecise, integer overflow disabled, inexact disabled	(no modifier)
	Imprecise, integer overflow enabled, inexact disabled	v
	Software, integer overflow enabled, inexact disabled	sv
	Software, integer overflow enabled, inexact enabled	svi

Table 4-1 lists the qualifier combinations that are supported by one or more of the individual instructions. The values in the Number column are referenced in subsequent sections to identify the combination of qualifiers accepted by the various instructions.

Table 4-1: Qualifier Combinations for Floating-Point Instructions

4.2    Floating-Point Load and Store Instructions

Floating-point load and store instructions load values and move data between memory and floating-point registers.

Table 4-2 lists the mnemonics and operands for instructions that perform floating-point load and store operations. The table is divided into groups of functionally related instructions. The operands specified within a particular group apply to all of the instructions contained in that group.

Table 4-2: Load and Store Instruction Formats

Table Notes:

1. In addition to the normal operands that can be specified with this instruction, relocation operands can also be specified (see Section 2.6.4).

Table 4-3 describes the operations performed by floating-point load and store instructions.

The load and store instructions are grouped by function. Refer to Table 4-2 for the instruction names.

Table 4-3: Load and Store Instruction Descriptions

4.3    Floating-Point Arithmetic Instructions

Floating-point arithmetic instructions perform arithmetic and logical operations on values in floating-point registers.

Table 4-4 lists the mnemonics and operands for instructions that perform floating-point arithmetic and logical operations. The table is divided into groups of functionally related instructions. The operands specified within a particular group apply to all of the instructions contained in that group.

The Qualifiers column in Table 4-4 refers to one or more trap or rounding modes as specified in Table 4-1.

Table 4-4: Arithmetic Instruction Formats

Table 4-5 describes the operations performed by floating-point load and store instructions. The arithmetic instructions are grouped by function. Refer to Table 4-4 for the instruction names.

Table 4-5: Arithmetic Instruction Descriptions

4.4    Floating-Point Relational Instructions

Floating-point relational instructions compare two floating-point values.

Table 4-6 lists the mnemonics and operands for instructions that perform floating-point relational operations. Each of the instructions can take an operand in any of the forms shown.

The Qualifiers column in Table 4-6 refers to one or more trap or rounding modes as specified in Table 4-1.

Table 4-6: Relational Instruction Formats

Table 4-7 describes the relational instructions supported by the assembler. The relational instructions are grouped by function. Refer to Table 4-6 for the instruction names.

Table 4-7: Relational Instruction Descriptions

4.5    Floating-Point Move Instructions

Floating-point move instructions move data between floating-point registers.

Table 4-8 lists the mnemonics and operands for instructions that perform floating-point move operations. The table is divided into groups of functionally related instructions. The operands specified within a particular group apply to all of the instructions contained in that group.

Table 4-8: Move Instruction Formats

Table 4-9 describes the operations performed by move instructions. The move instructions are grouped by function. Refer to Table 4-8 for the instruction names.

Table 4-9: Move Instruction Descriptions

4.6    Floating-Point Control Instructions

Floating-point control instructions test floating-point registers and conditionally branch.

Table 4-10 lists the mnemonics and operands for instructions that perform floating-point control operations. The specified operands apply to all of the instructions listed in the table.

Table 4-10: Control Instruction Formats

Table 4-11 describes the operations performed by control instructions. The control instructions are grouped by function. Refer to Table 4-10 for instruction names.

Table 4-11: Control Instruction Descriptions

4.7    Floating-Point Special-Purpose Instructions

Floating-point special-purpose instructions perform miscellaneous tasks.

Table 4-12 lists the mnemonics and operands for instructions that perform floating-point special-purpose operations.

Table 4-12: Special-Purpose Instruction Formats

Table 4-13 describes the operations performed by floating-point special-purpose instructions.

Table 4-13: Control Register Instruction Descriptions